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4-1531 august 1997 hi5710a 10-bit, 20 msps a/d converter features resolution 0.5 lsb (dnl) . . . . . . . . . . . . . . . . . . 10-bit maximum sampling frequency . . . . . . . . . . . 20 msps low power consumption (reference current excluded) . . . . . . . . . . . . . .150mw standby mode power . . . . . . . . . . . . . . . . . . . . . . .5mw no sample and hold required ttl compatible inputs three-state ttl compatible outputs single +5v analog power supply single +3.3v or +5v digital power supply applications video digitizing - multimedia data communications image scanners medical imaging video recording equipment camcorders qam demodulation description the hi5710a is a low power, 10-bit, cmos analog-to-digital converter. the use of a 2-step architecture realizes low power consumption, 150mw, and a maximum conversion speed of 20mhz with only a 3 clock cycle data latency. the hi5710a can be powered down, disabling the chip and the digital outputs, reducing power to less than 5mw. a built-in, user controllable, calibration circuit is used to provide low linearity error, 1 lsb. the low power, high speed and small package outline make the hi5710a an ideal choice for ccd, battery, and high channel count applications. the hi5710a does not require an external sample and hold but requires an external reference and includes force and sense reference pins for increased accuracy. the digital out- puts can be inverted, with the msb controlled separately, allowing for various digital output formats. the hi5710a includes a test mode where the digital outputs can be set to a ?ed state to ease in-circuit testing. pinout hi5710a (mqfp) top view ordering information part no. temp. range ( o c) package pkg. no. HI5710AJCQ -20 to 75 48 ld mqfp q48.7x7-s 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 avss v rb v rb nc nc nc v rt v rt av ss av ss av dd av dd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 dv ss dv dd dv ss nc nc dv dd av ss ts cal nc v in at tstr av ss to tin reset dv ss sel av dd testmode linv minv clk oe ce file number 3921.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright ?intersil corporation 1999
4-1532 functional block diagram 30 29 39 s/h amp course comparator and encode dac + - 8 x fine comparator and encode calibration unit course correction and latch fine latch 8 12 10 9 11 1 5 3 2 4 15 41 17 19 21 20 24 22 23 35 34 timing gen d9 (msb) d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) minv linv testmode cal sel reset v in v rt v rt v rb v rb clk ce oe auto calibration pulse generator hi5710a
4-1533 absolute maximum ratings t a =25 o c thermal information supply voltage, av dd , dv dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v reference voltage, v rt , v rb . . . . . . . . . v dd + 0.5v to v ss - 0.5v analog input voltage, v in . . . . . . . . . . . . . v dd + 0.5v to v ss - 0.5v digital input voltage, v ih , v il . . . . . . . . . . v dd + 0.5v to v ss - 0.5v digital output voltage, v oh , v ol . . . . . . . v dd + 0.5v to v ss - 0.5v thermal resistance (typical, note 1) ja ( o c/w) mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range, t stg . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (lead tips only) operating conditions supply voltage av dd , av ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 0.25v dv dd , dv ss . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3v to 5v 0.25v |dgnd-agnd| . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mv to 100mv reference input voltage v rb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8v to 2.8v v rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.6v to 4.6v analog input range, v in . . . . . . . .(v rt - v rb ) (1.8v p-p to 2.8v p-p ) clock pulse width t pw1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25ns (min) t pw0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25ns (min) temperature, t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20 o c to 75 o c caution: stresses above those listed in ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations f c = 20 msps, av dd = +5v, dv dd = +3.3v, v rb = 2.0v, v rt = 4.0v, t a = 25 o c (note 2) parameter test conditions min typ max unit system performance offset voltage e ot 40 90 140 mv e ob -120 -70 -20 mv integral non-linearity, inl v in = 2.0v to 4.0v - 1.3 2.0 lsb differential non-linearity, dnl - 0.5 1.0 lsb dynamic characteristics maximum conversion speed, f c f in = 1khz ramp 20 - - msps minimum conversion speed, f c - - 0.5 msps effective number of bits, enob f in = 3mhz - 8.7 - bits signal to noise and distortion, sinad f in = 100khz - 53 - db f in = 500khz - 52 - db f in = 1mhz - 53 - db f in = 3mhz - 54 - db f in = 7mhz - 47 - db f in = 10mhz - 45 - db spurious free dynamic range, sfdr f in = 100khz - 60 - db f in = 500khz - 59 - db f in = 1mhz - 60 - db f in = 3mhz - 65 - db f in = 7mhz - 50 - db f in = 10mhz - 49 - db differential gain error, dg ntsc 40 ire mod ramp, f c = 14.3 msps - 1.0 - % differential phase error, dp - 0.3 - degree hi5710a
4-1534 analog inputs analog input bandwidth (-3db), bw - 100 - mhz analog input current v in = 4v - - 50 a v in = 2v -50 - - a analog input capacitance, c in v in = 2.5v + 0.07v rms -9-pf reference input reference pin current, i rt reset = low 5 7 11 ma reference pin current, i rb reset = low -11 -7 -5 ma reference resistance (v rt to v rb ), r ref 180 280 380 ? digital inputs digital input voltage v ih av dd = 4.75v to 5.25v 2.3 - - v v il - - 0.80 v digital input current i ih dv dd = max v ih = dv dd --5 a i il v il = 0v - - 5 a digital outputs digital output current i oh oe = av ss , dv dd = min v oh = dv dd -0.5v 3.5 - - ma i ol v ol = 0.4v 3.5 - - ma digital output leakage current i ozh oe = av dd , dv dd = max v oh = dv dd --1 a i ozl v ol = 0v - - 1 a timing characteristics output data delay, t dl load is one ttl gate 8 13 18 ns output enable/disable delay t pzl 10 15 20 ns t plz 20 25 30 ns t pzh 10 15 20 ns t phz 20 25 30 ns sampling delay, t sd 246ns power supply characteristic analog supply current, ia dd f in = 1khz ramp wave input 20 27 34 ma digital supply current, id dd -35ma analog standby current ce = high - - 1.0 ma digital standby current - - 1.0 a note: 2. electrical specifications guaranteed only under the stated operating conditions. electrical speci?ations f c = 20 msps, av dd = +5v, dv dd = +3.3v, v rb = 2.0v, v rt = 4.0v, t a = 25 o c (note 2) (continued) parameter test conditions min typ max unit hi5710a
4-1535 timing diagrams figure 1. figure 2. t pw1 t pw0 clock analog input data output n n + 1 n + 2 n + 3 n + 4 t dl n - 3 n - 2 n - 1 n t sd = indicates point at which analog data is sampled 1.65v 1.65v 1.65v (dv dd = 3.3v) 2.5v (dv dd = 5.0v) t pzl t pzh 1.65v (dv dd = 3.3v) 2.5v (dv dd = 5.0v) t plz t phz 1.65v (dv dd = 3.3v) 2.5v (dv dd = 5.0v) data output active high impedance output enable ( oe) hi5710a
4-1536 calibration timing diagrams figure 3. external calibration pulse timing diagram figure 4a. calibration during h sync figure 4b. calibration during v sync figure 4. examples of external calibration pulse input for video applications 10ns or more 7 clocks 1 clock or more clk cal d5 to d9 d0 to d4 input clk cal input clk cal hi5710a
4-1537 typical performance curves figure 5. supply current vs ambient temperature figure 6. maximum operating frequency vs ambient temperature figure 7. output data delay vs ambient temperature figure 8. sampling delay vs ambient temperature figure 9. sinad vs input frequency figure 10. sfdr vs input frequency supply current (ma) 28 27 26 25 24 -20 0 25 50 75 ambient temperature ( o c) f c = 20mhz f in = 1khz ramp wave av dd = 5.0v dv dd = 3.3v 100 35 30 25 20 maximum operating frequency (mhz) f in = 1khz ramp wave av dd = 5.0v dv dd = 3.3v -20 0 25 50 75 ambient temperature ( o c) 100 -20 0 25 50 75 ambient temperature ( o c) 17 19 15 13 output data delay (ns) 11 av dd = 5.0v dv dd = 3.3v f c = 1mhz c l = 20pf ambient temperature ( o c) -20 0 25 50 75 av dd = 5.0v dv dd = 3.3v f c = 1mhz 6 8 4 2 sampling delay (ns) 65 60 55 50 45 40 35 30 25 0.1 1 10 100 input frequency (mhz) sinad (db) av dd = 5.0v dv dd = 3.3v f c = 20mhz v in = 2v p-p t a = 25 o c dv dd = 3.3v dv dd = 5v 80 75 70 65 60 55 50 45 40 35 30 sfdr (db) 0.1 1 10 100 input frequency (mhz) av dd = 5.0v dv dd = 3.3v f c = 20mhz v in = 2v p-p t a = 25 o c hi5710a
4-1538 figure 11. effective bits vs input frequency figure 12. input bandwidth figure 13. analog input current vs input voltage figure 14. enob vs clock frequency figure 15. thd vs input frequency figure 16. snr vs input frequency typical performance curves (continued) effective number of bits (bits) 10 9 8 7 6 5 4 0.1 1 10 100 input frequency (mhz) dv dd = 5v dv dd = 3.3v av dd = 5.0v dv dd = 3.3v f c = 20mhz v in = 2v p-p t a = 25 o c input frequency (hz) 100k 1m 10m av dd = 5.0v dv dd = 3.3v f c = 20mhz v in = 2v p-p t a = 25 o c 100m 1 0 -1 -2 -3 output level (db) 2 -4 -5 80 60 40 20 0 -20 -40 -60 -80 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 input voltage (v) input current (ma) t a = 25 o c clock frequency effective number of bits (bits) 10 9.5 9 8.5 8 7.5 6.5 6 51015202530 7 f in = 1mhz dv dd = 5v/3.3v f in = 5mhz dv dd = 5v f in = 5mhz dv dd = 3.3v input frequency (mhz) thd (db) -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 0.1 1 10 100 dv dd = 3.3v dv dd = 5v snr (db) input frequency (mhz) 59 57 55 53 51 49 47 45 100 1,000 10,000 100,000 dv dd = 3.3v dv dd = 5v hi5710a
4-1539 pin description and i/o pin equivalent circuit pin number symbol equivalent circuit description 1 to 5, 8 to 12 d0 to d9 digital outputs: d0 (lsb) to d9 (msb). 13 to test pin, leave pin open. 7, 45 dv dd digital v dd . 6, 16, 48 dv ss digital v ss . 27, 28, 36, 43, 44 av ss analog v ss . 17 sel controls calibration input pulse selection after completion of the internal start-up calibration function. high: selects the internal auto calibration pulse generation function low: selects the external calibration pulse input, cal pin 41. 22 clk clock pin. 41 cal calibration pulse input, calibration starts on a falling edge, normally high. 15 reset calibration circuit reset and internal calibration function restart, resets with a negative pulse, normally high. 14 tin factory test signal input, normally tied to av ss or av dd . d1 dv dd dv ss 17 av dd av ss 22 av ss av dd 41 av ss av dd 15 av ss av dd hi5710a
4-1540 29, 30 v rt reference top, normally 4.0v. 34, 35 v rb reference bottom, normally 2.0v. 38 at factory test signal output, leave pin open. 42 ts factory test signal input, tie to av dd . 37 tstr factory test signal input, tie to av ss . 23 oe d0 to d9 output enable. low: outputs enabled. high: high impedance state. 24 ce chip enable. low: active state. high: standby state. 19 testmode test mode. high: normal output state. low: output ?ed. 20 linv output inversion. high: d0 to d8 are inverted. low: d0 to d8 are normal. pin description and i/o pin equivalent circuit (continued) pin number symbol equivalent circuit description av dd av ss 29, 30 34, 35 23 av ss av dd 24 av ss av dd 19 av ss av dd 20 av ss av dd hi5710a
4-1541 21 minv output inversion. high: d9 is inverted. low: d9 is normal. 18, 25, 26 av dd analog v dd . 39 v in analog input. a/d output code table input signal voltage step digital output code msb lsb v rt 1023 11111111111 512 10000000000 511 01111111111 v rb 0 00000000000 note: 3. this table shows the correlation between the analog input voltage and the digital output code. (testmode = 1, minv and linv= 0) digital output data format table testmode linv minv d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 1 0 0 nnnnnnnnnn 1 1 0 iiiiiiiiin 1 0 1 nnnnnnnnn i 1 1 1 iiiiiiiiii 0 0 0 1010101010 0 1 0 0101010100 0 0 1 1010101011 0 1 1 0101010101 notes: 4. this table shows the output state for the combination of testmode, linv, and minv states. 5. n: non-inverted output. 6. i: inverted output. pin description and i/o pin equivalent circuit (continued) pin number symbol equivalent circuit description 21 av ss av dd 39 av ss + - av dd hi5710a
4-1542 detailed description the hi5710a is a two step a/d converter featuring a 5-bit upper comparator group and a 5-bit lower comparator group. a user controllable internal calibration unit is used to improve linearity. the voltage references must be supplied externally, with v rb and v rt typically being set to 2.0v and 4.0v respectively. both chip enable and output enable pins are provided for ?xibility and to reduce power consumption. the digital outputs can be inverted by control inputs linv and minv, where linv controls outputs d0 through d8 and minv con- trols output d9 (msb). this allows for various digital output data formats, such as straight binary, inverted binary, offset twos complement or inverted offset twos complement. analog input the analog input typically requires a 2v p-p full scale input signal. the full scale input can range from 1.8v p-p to 2.8v p-p dependent on the voltage references used. the input capacitance is small when compared with other ?sh type a/d converters. however, it is necessary to drive the input with an ampli?r with suf?ient bandwidth and drive capability. op amps such as the ha5020 should make an excellent input ampli?r depending on the application requirements. in order to prevent parasitic oscillation, it may be necessary to insert a resistor between the output of the ampli?r and the a/d input. be sure to consider the ampli?rs settling time in ccd applications or where step inputs are expected. reference input the analog input voltage range of the a/d is set by the voltage difference between the v rt and v rb voltage references. the hi5710a is designed for use with external voltage references of 2.0v and 4.0v on v rb and v rt , respectively. the analog input voltage range of the a/d will now be from 2.0v to 4.0v. the v rb voltage reference range is 1.8v to 2.8v and the v rt voltage reference range is 3.6v to 4.6v. the voltage difference between the v rt and v rb voltage references, (v rt - v rb ), can range from 1.8v to 2.8v. the v rt and v rb voltage reference input pins must be decoupled to analog ground to minimize noise on these references. a 0.1 f capacitor is usually adequate. clock input the hi5710a samples the input signal on the rising edge of the clock with the digital data being latched at the digital outputs (d0 - d9) after 3 clock cycles. the hi5710a is designed for use with a 50% duty cycle square wave, but a 10% variation should not affect performance. the clock input can be driven from +3.3v cmos or +5v ttl/cmos logic. when using a +3.3v digital supply, hc or ac cmos logic will work well. digital inputs the digital inputs can be driven from +3.3v cmos or +5v ttl/cmos logic. when using a +3.3v digital supply, hc or ac cmos logic will work well. digital outputs the digital outputs are cmos outputs. the linv control input will invert outputs d0 through d8 and minv control input will invert output d9 (msb). this allows the user to set the digital output data for a number of different digital for- mats. the outputs can also be three-stated by pulling the oe control input high. the digital output supply can run from +3.3v or +5v. the digital outputs will generate less radiated noise using +3.3v, but the outputs will have less drive capability. the digital outputs will only swing to dv dd , therefore exercise care if interfacing to +5v logic when using a +3.3v supply. the digital output data can also be set to a ?ed, predetermined state, through the use of the testmode, linv and minv control input signals, see the digital output data format table. by setting the testmode pin low, the outputs go to a de?ed digital pattern. this pattern is varied by the minv and linv control inputs. this feature can be used for in-circuit testing of the digital output data bus. calibration function the hi5710a has a built-in calibration unit which is designed to provide superior linearity by correcting the gain error of the subrange ampli?ation circuitry. in addition to the calibration unit, the hi5710a provides a built-in auto calibration pulse generation function. figure 20 shows a functional block diagram of the auto calibration pulse generator circuit. the calibration pulse generation functions provided can be subdivided into four operational areas. the ?st function is the generation of the calibration pulses required to complete the initial (power-up) calibration process when power is ?st supplied to the converter. the next two functions accommo- dated are the generation of periodic calibration pulses, either internally or externally, to maintain calibration. the last function is the provision for externally initiating or re-initiating the power-up calibration process. power-up calibration function the initial power-up calibration requires over 600 calibration pulses in order to complete the calibration process when power is ?st applied to the converter. the power-up calibra- tion function provided by the auto calibration pulse generator automatically generates these pulses internally and completes the initial calibration process. the following ?e conditions must be satis?d in order for the auto calibration pulse generator power-up calibration process to be initiated : a) the voltage between av dd and av ss is approximately 2.5v or more. b) the voltage between v rt and v rb is approximately 1.0v or more. c) the reset control input pin (pin 15) must be high (logic 1). d) the ce control input pin (pin 24) must be low (logic 0). e) condition b must be met after condition a. once all ?e of these conditions is satis?d the power-up calibration pulses are generated. these power-up calibration pulses are derived from a divided-by sixteen sample clock hi5710a
4-1543 (clk/16). a 14-bit counter is also counting the clk/16 signal and when the 14-bit counter reaches the end of its count range the carry out from the counter is used to gate off or mask the clk/16 power-up calibration pulses. the time required for the power-up calibration process to be completed after the above ?e conditions has been met can be calculated using the following equation: t power-up cal = (2 4 x 2 14 )/(f clk ) = 2 18 /f clk . for example, if the sample clock frequency is 20mhz, the time required for the power-up calibration process to be completed, after the above ?e conditions has been met, is t power-up cal = 2 18 /f clk = 2 18 /20x10 6 = 262,144/20 x 10 6 , t power-up cal = 13.1ms. auto calibration pulse generation function the auto calibration pulse generator provides the user with the choice of internal or external periodic calibration pulse generation following the completion of the power-up calibra- tion process. the selection of internal or external periodic calibration pulse generation is made through the use of the sel control input pin (pin 17). setting the sel control input pin high (logic 1) selects the internal periodic calibration pulse generation function. setting the sel control input pin low (logic 0) selects the external calibration pulse input pin (cal, pin 41). for the case where the internal periodic calibration pulse generation function has been chosen, sel control input pin high, the auto calibration pulse generator periodically gener- ates calibration pulses internally so that calibration is per- formed constantly without the need to provide calibration input pulses from an external source. these periodic calibra- tion pulses are derived from the divided-by sixteen sample clock (clk/16). the clk/16 signal drives a 24-bit counter which generates a carry-out that is used as the internal cali- bration pulse. the time between calibration pulses when using the internal auto calibration pulse generator can be calculated using the following equation: t internal cal pulse = (2 4 x 2 24 )/(f clk ) = 2 28 /f clk . for example, if the sample clock frequency is 20mhz, the time between internal auto calibration pulses is: t internal cal pulse =2 28 /f clk =2 28 /20 x 10 6 = 268,435,456/20 x 10 6 , t internal cal pulse = 13.4s. since a calibration is completed once every seven calibration pulses, the time required to complete a calibration cycle is: t internal cal cycle = (7 x 2 28 )/f clk . therefore, if the sample clock frequency is 20mhz, the inter- nal calibration cycle is: t internal cal cycle = (7 x 2 28 )/20 x 10 6 = 93.95s. it should be noted that this method of periodic calibration may not be acceptable if the ?ing of the lower ?e output bits during the calibration (see the discussion below on external calibration pulse input function) would cause problems since the calibration is executed asynchronously without regard to the analog input signal. external calibration pulse input function if the auto calibration pulse generation function cannot be used then periodic calibration can be performed by providing externally input calibration pulses to the cal input pin (pin 41) and setting the sel control input pin (pin 17) low. refer to figure 3, external calibration pulse timing diagram, for details on the required timing of the externally supplied calibration pulses. a setup time of 10ns or longer is required for the cal input and it must stay low for at least one sample clock (clk) period. calibration starts when the falling edge of the exter- nally supplied calibration pulse, input to the cal pin, is detected. one calibration is completed in 11 sample clock cycles. seven sample clock cycles after the falling edge of the externally supplied calibration pulse is detected, the calibration circuit takes exclusive possession of the lower comparators, d0 through d4, for four sample clock cycles. during this time, the d0 through d4 outputs are latched with the previous data (cycle seven data). the upper 5 bits, d5 through d9, will operate as usual during the calibration. the calibration must be done when the part is ?st powered up, if the sampling frequency changes, when the supplies vary more than 100mv or when (v rt -v rb ) changes more than 200mv. figure 4 shows several possible external calibration pulse timing schemes where the calibration is performed outside the active video interval by using the video sync signal as the externally supplied cal input. it is not necessary to calibrate as often as these ?ures show, these are only design ideas. it is also possible to use only the power-up calibration function by leaving the sel control input pin (pin 17) low and ?ing the cal input pin (pin 41) either high or low. note, however, that using only the power-up calibration function will require the above restrictions on the sample frequency and the ?ctuation range of the power supply voltage and the reference voltage differential be maintained. initiating/re-initiating power-up calibration function the power-up calibration function can be initiated/re-initiated after the power supply voltage and the reference voltages are stabilized by using the ce (pin 24) or reset (pin 15) control input pins. this might prove useful in a situation where the turn-on characteristics of the power supply and reference voltages is unstable/indeterminate or where the sequence of power-up does not meet the required conditions stated earlier. power, grounding, and decoupling to reduce noise effects, keep the analog and digital grounds separated. bypass both the digital and analog v dd pins to their respective grounds with a ceramic 0.1 f capacitor close to the input pin. a larger capacitor (1 f to 10 f) should be placed somewhere on the pc board for low fre- quency decoupling of both analog and digital supplies. the analog supply should be present before the digital supply to reduce the risk of latch-up. the digital supply can run from +3.3v or +5v. a +3.3v supply generates less radiated noise at the digital outputs, but results in less drive capability. the speci?ations do not change with digital supply levels. remember, the digital outputs will only swing to dv dd . hi5710a
4-1544 to obtain full expected performance from the converter be sure that the circuit board has a large ground plane to provide as low an impedance as possible. it is recommended that the converter be mounted directly to the circuit board and the use of a socket is highly discouraged. test circuits figure 17. integral and differential non-linearity error test circuit figure 18. maximum operational speed and differential gain /phase error test circuit figure 19a. figure 19b. figure 19. digital output test circuit - v in hi5710a dut 10 clk (20mhz) + a < b a > b comparator a10 a1 a0 b10 b1 b0 ? ? 10 s1 s2 -v +v s1: on if a < b s2: on if a > b buffer dvm controller 10 to 111 ???10 000 ???00 signal source ntsc sg v in 10 scope vector dg sg (cw) amp hi5710a dut d/a 12-bit clk 1 2 1 2 scope dp f c -40 0 100 ire sync burst 2.0v 4.0v 40 ire modulation 2v 4v f c -1khz v rt v in v rb clk oe gnd v dd 2v 4v v ol i ol + - v rt v in v rb clk oe gnd v dd 2v 4v v oh i oh + - hi5710a
4-1545 figure 20. calibration pulse generation circuit typical application circuits figure 21a. power-up calibration with internal auto calibration selected test circuits (continued) 14-bit counter clr co 1 16 24-bit counter clr co sence amp 1 av dd av ss reset ce sence amp 2 v rt v rb d clr q av dd out sel cal clk avss v rb v rb nc nc nc v rt v rt av ss av ss av dd av dd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 dv ss dv ss nc nc dv dd av ss ts cal nc v in at tstr av ss to tin reset dv ss sel av dd testmode linv minv clk oe ce 12345678 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9101112 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 +5va 0.1 +3.3vd 10 f 0.1 f + - 2.0v + - 4.0v +5va 0.1 f 0.1 f 10 f +5va 4.0v 2.0v digital outputs clock input av ss dv ss +3.3vd 0.1 hi5710a hi5710a
4-1546 figure 21b. power-up calibration with external calibration pulse input selected typical application circuits (continued) avss v rb v rb nc nc nc v rt v rt av ss av ss av dd av dd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 dv ss dv ss nc nc dv dd av ss ts cal nc v in at tstr av ss to tin reset dv ss sel av dd testmode linv minv clk oe ce 12345678 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9101112 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 +5va 0.1 +3.3vd 10 f 0.1 f calibration + - 2.0v + - 4.0v +5va 0.1 f 0.1 f 10 f +5va 4.0v 2.0v digital outputs clock input av ss dv ss pulse +3.3vd 0.1 hi5710a hi5710a
4-1547 figure 21c. only power-up calibration being utilized typical application circuits (continued) avss v rb v rb nc nc nc v rt v rt av ss av ss av dd av dd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 dv ss dv ss nc nc dv dd av ss ts cal nc v in at tstr av ss to tin reset dv ss sel av dd testmode linv minv clk oe ce 12345678 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9101112 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 +5va 0.1 +3.3vd 10 f 0.1 f + - 2.0v + - 4.0v +5va 0.1 f 0.1 f 10 f +5va 4.0v 2.0v digital outputs clock input av ss dv ss +3.3vd 0.1 hi5710a hi5710a
4-1548 timing de?itions sampling delay, is the time delay between the external sample command (the rising edge of the clock) and the time at which the analog input signal is actually sampled. this delay is due to internal clock path propagation delays. data latency, after the analog sample is taken, the digital representation is output on the digital data output bus after the 3rd cycle of the clock. this is due to the pipeline nature of the converter where the data has to ripple through the stages. this delay is speci?d as the data latency. after the data latency time, the data representing each succeeding analog input sample is output on the following rising edge of the clock pulse. the digital data output lags the analog input sample by 3 sampling clock cycles. power-up initialization, this time is de?ed as the maximum number of clock cycles that are required to initialize the converter at power-up. the requirement arises from the need to initialize some dynamic circuits within the converter. static performance de?itions differential linearity error, dnl, is the worst case deviation of a code width from the ideal value of 1 lsb. the converter is guaranteed to have no missing codes over the operating temperature range. integral linearity error, inl, is the worst case deviation of a code center from a best ? straight line calculated from the measured data. dynamic performance de?itions fast fourier transform (fft) techniques are used to evaluate the dynamic performance of the hi5710a. a low distortion sine wave is applied to the input, it is sampled, and the output is stored in ram. the data is then transformed into the frequency domain with a 2048 point fft and ana- lyzed to evaluate the dynamic performance of the a/d. the analog sine wave input signal to the converter is -0.5db down from full scale for all these tests. the distortion num- bers are quoted in dbc (decibels with respect to carrier) and do not include any correction factors for normalizing to full scale. signal-to-noise ratio, snr, is the measured rms signal to rms noise for a speci?d analog input frequency and sampling frequency. the noise is the rms sum of all of the spectral components excluding the fundamental and the ?st ?e harmonics. signal-to-noise + distortion ratio, sinad, is the measured rms signal to rms sum of all other spectral components below the nyquist frequency excluding dc. effective number of bits, enob, the effective number of bits (enob) is calculated from the measured sinad data. as follows: enob = (sinad - 1.76 + v corr ) / 6.02, where: v corr = 0.5db. v corr adjusts the enob for the amount the analog input signal is below full scale. 2nd and 3rd harmonic distortion, is the ratio of the rms value of the 2nd and 3rd harmonic component, respectively, to the rms value of the measured input signal. analog input bandwidth, is the frequency at which the amplitude of the digitally reconstructed output has decreased 3db below the amplitude of the input sine wave. the input sine wave has a peak-to-peak amplitude equal to the differential reference voltage. the bandwidth given is measured at the speci?d sampling frequency. hi5710a
4-1549 figure 22. 10-bit video imaging components figure 23. 10-bit communications components hfa1135 hfa1245 ha5020 hi5710a hi5767/2 hi5767/4 hsp9501 hsp48410 hsp48908 hsp48212 hsp43891 hsp43168 hsp43216 hi1171 hi3050 hi3338 ha5020 ha2842 hfa1115 hfa1135: 350mhz op amp with output limiting hfa1245: dual 350mhz op amp with disable/enable ha5020: 100mhz video op amp hi5710a: 10-bit, 20 msps, a/d converter hi5767/2/4: 10-bit, 20/40 msps, low power a/d converter with internal reference hsp9501: programmable data buffer hsp48410: histogrammer/accumulating buffer, 10-bit pixel resolution hsp48908: 2-d convolver, 3 x 3 kernal convolution, 8-bit hsp48212: digital video mixer hsp43891: digital filter, 30mhz, 9-bit hsp43168: dual fir filter, 10-bit, 33mhz/45mhz hsp43216: digital half band filter hi1171: 8-bit, 40mhz, video d/a converter hi3338: 8-bit, 50mhz, video d/a converter hi3050: triple 10-bit, 50mhz, video dac ha2842: high output current, video op amp hfa1115: 350mhz programmable gain buffer with output limiting cmos logic available in hc, hct, ac, act, and fct. hfa3600 hfa3102 hfa3101 hfa1100 hi5710a hi5767/2 hi5767/4 hsp43168 hsp43216 hsp43891 hsp50016 hsp50110 hsp50210 hi5721 hi20201 hi20203 hi5780 hfa1115 hfa3600: low noise amplifier/mixer hfa3102: dual long-tailed pair transistor array hfa3101: gilbert cell transistor array hfa1100: 850mhz op amp hi5710a: 10-bit, 20 msps, a/d converter hi5767/2/4: 10-bit, 20/40 msps, low power a/d converter with internal reference hsp43168: dual fir filter, 10-bit, 33mhz/45mhz hsp43216: digital half band filter hsp43891: digital filter, 30mhz, 9-bit hsp50016: digital down converter hsp50110: digital quadrature tuner hsp50210: digital costas loop hi5721: 10-bit, 100mhz, communications d/a converter hi5780: 10-bit, 80mhz cmos d/a converter hi20201: 10-bit, 160mhz, high speed d/a converter hi20203: 8-bit, 160mhz, high speed d/a converter hfa1115: 350mhz programmable gain buffer with output limiting cmos logic available in hc, hct, ac, act, and fct. dsp/ p amp amp d/a a/d dsp/ p amp amp d/a a/d hi5710a
4-1550 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hi5710a

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